Nvidia is opening its data center architecture to AI processors developed by other chipmakers.
U.S. AI chip startup d-Matrix said on Sept. 10 that its next-generation Raptor XPU will connect directly to Nvidia MGX rack-scale infrastructure through NVLink Fusion. Raptor is expected to complete its final design by the end of 2026, with initial MGX-based systems targeted for the fourth quarter of 2027.
The significance lies in the type of processor entering Nvidia's infrastructure. Raptor is designed specifically for generative AI inference, the process of running trained models to generate responses. Nvidia is connecting the third-party accelerator to its interconnect, networking and rack architecture, allowing different types of AI processors to operate within the same data center system.
Inference Is Changing AI Chip Architecture
As AI moves deeper into commercial deployment, inference workloads are growing rapidly. Chatbots generate output with every user request, coding agents repeatedly call models while completing tasks, and voice agents require responses with near-real-time latency.
Processing speed, memory efficiency, power consumption and cost per token have a direct impact on the economics of AI services. This is creating demand for processors optimized for specific inference workloads.
d-Matrix is targeting this market with Raptor. The processor uses a memory-centric architecture that combines DRAM memory and SRAM compute dies in a three-dimensional design. The company says the architecture is intended to reduce bottlenecks associated with moving data between memory and processors, targeting applications such as coding assistants, real-time chatbots and voice agents.
Nvidia GPUs and Raptor Can Split the Same AI Workload
One of the most significant elements of the Nvidia-d-Matrix collaboration is the ability to divide an inference workload between different processors. Generative AI inference can be separated into two major stages. The prefill stage processes a user's input and context and typically requires substantial computing capacity. The decode stage generates output token by token, where latency and memory efficiency become critical.
Under the architecture proposed by d-Matrix, Nvidia's Vera Rubin platform can handle compute-intensive prefill workloads while Raptor handles latency-sensitive decoding. Nvidia processors and a third-party inference accelerator can therefore work on different stages of the same AI service.
NVLink Fusion provides the connection between these computing environments. Raptor is designed to operate in an Nvidia MGX rack alongside Vera CPUs, NVLink switches, BlueField-4 DPUs, ConnectX-9 SuperNICs and Spectrum-X Ethernet networking.
Nvidia Expands the Role of NVLink
Nvidia introduced NVLink Fusion to allow outside chipmakers and cloud providers to connect custom CPUs and AI accelerators to its data center infrastructure. The ecosystem already includes semiconductor and technology companies working on custom processors, connectivity and chip design.
d-Matrix extends that approach into specialized inference processors. For d-Matrix, integration with Nvidia infrastructure provides access to an established rack and networking environment without requiring an entirely separate data center system around Raptor.
For Nvidia, the arrangement keeps its infrastructure relevant as data centers adopt a wider range of AI processors. NVLink becomes a connection point between Nvidia's processors and third-party accelerators.
That gives Nvidia another way to retain a role in AI infrastructure even as hyperscalers and chip startups develop processors optimized for specific workloads.
AI Chip Competition Expands to the System Level
AI data center performance increasingly depends on how processors, memory and networks operate together. CPUs, GPUs, inference accelerators and memory must exchange large volumes of data with low latency, while power delivery and cooling must support the entire system.
Nvidia's MGX architecture reflects this approach. The modular platform supports combinations of GPUs, CPUs, DPUs and networking technologies across server and rack-scale AI systems. Adding Raptor extends that modular structure to a specialized third-party inference processor.
The competitive field is consequently widening. Processor performance remains critical, while interconnects, memory architecture, networking and packaging increasingly determine how efficiently a data center can run AI workloads.
This is particularly important for inference. As AI services scale to millions of users and autonomous agents make repeated model calls, the cost of moving data and generating each token becomes part of the operating economics of AI.
What the Shift Means for Korean Chipmakers
The change also matters for Samsung Electronics and SK hynix. Korean semiconductor companies hold important positions in AI infrastructure through high-bandwidth memory, advanced memory, foundry manufacturing and advanced packaging. A broader market for inference-focused XPUs and custom ASICs could increase the number and variety of processors requiring high-performance memory.
Architectures such as Raptor also highlight the growing importance of reducing the distance and energy required to move data between compute and memory. That puts memory performance, advanced packaging and chip interconnects closer to the center of AI system design.
For Samsung, the shift could create opportunities spanning foundry manufacturing, memory and advanced packaging. For SK hynix, a wider range of AI processors could eventually expand the customer base for high-performance memory.
Those opportunities should not yet be treated as direct commercial gains. Raptor remains under development, and its eventual customers and memory supply structure have not been established.
The larger signal for Korea is the changing architecture around AI processors. Chipmakers will increasingly need to track what memory new XPUs use, how the processors are packaged and how they connect inside rack-scale systems.
Nvidia's Next Position in the AI Stack
Raptor has yet to prove itself commercially. d-Matrix expects to complete the chip's final design by the end of this year, while initial availability of NVLink Fusion-enabled MGX systems is targeted for the fourth quarter of 2027. Performance, pricing and customer adoption will determine its market impact.
The partnership nevertheless shows where Nvidia is placing its next bet. As specialized inference processors enter AI data centers, Nvidia wants NVLink, networking and rack infrastructure to connect them. The influence Nvidia built around GPUs is now extending into the architecture that connects AI systems. The d-Matrix partnership offers an early view of that strategy.
